1. Field of the Invention
The present invention relates in general to graphics systems and in particular to a method and apparatus for resetting a video SRAM within a single DRAM-SRAM transfer cycle in a graphics system.
2. Description of Prior Art
A graphics system typically comprises a central processing unit (CPU), a memory and a video display (CRT).
In operation, data to be displayed on the CRT is transferred from the CPU to the memory and then onto the CRT. To maintain the display on the CRT, the data in the memory is repeatedly transferred to the CRT in what are called screen refresh cycles. New data or a change in the data to be displayed on the CRT is transferred to the memory in what are called update cycles. The refresh cycles always take priority over the update cycles.
In the initial development of graphics systems, the memory typically comprised a single dynamic random access memory (DRAM) which was used both for refreshing the screen and for receiving video updates. However, because of the priority given to the refresh function, the update of the DRAM was constrained to those periods of time when the CRT was in a blanking cycle, i.e. returning to its initial state after scanning a line or returning to its initial state at the end of a frame scan. As a result, the updating of the DRAM was typically limited to a period of approximately 13% of the DRAM operating time.
To isolate the refresh and updating functions of the then current video graphics systems and to thereby increase the time available for updating the DRAM and for freeing the DRAM for use in other data processing operations, an improvement in video graphic systems was made comprising the use of a static random access memory (SRAM) in combination with a DRAM. In the improved system there was provided a CPU, a DRAM input register, a DRAM, a DRAM output register, data transfer gates, an SRAM and an SRAM output register.
In operation, video data for updating the DRAM is transferred from the CPU to the DRAM input register and then to the DRAM. From the DRAM, the data may be transferred to the DRAM output register and back to the CPU for further processing or, via the transfer gates, in parallel to the SRAM. From the SRAM the data is transferred to the SRAM output register for use in refreshing the CRT.
In practice, the data for updating the DRAM is serially transferred from the CPU to the DRAM. For a DRAM comprising 256 rows, a complete data transfer requires 256 DRAM cycles. The data transfer from the DRAM to the SRAM being in parallel requires 1 DRAM cycle, for a total of 257 DRAM cycles.
An example of the above-described improved DRAM-SRAM graphics system is disclosed in U.S. patent application Ser. No. 564,969, filed Dec. 23, 1983, entitled Improved Semiconductor Device for Serial Scan Applications and assigned to the assignee of the present application.
In still another improvement in video graphics systems, an SRAM input register is provided for use between an external source of video data and an SRAM.
In operation, video data from the external source is transferred from the source to the SRAM input register. From the SRAM input register, the data is transferred serially into the SRAM. For an SRAM comprising 256 column cells, the serial transfer requires 256 SRAM cycles.
Data transfers using SRAM cycles are typically faster than data transfers using DRAM cycles. For example, in a typical serial SRAM data transfer, the data transfer is 4 times faster than a typical serial DRAM data transfer. Accordingly, a 256 step serial SRAM data transfer requires only 64 DRAM cycle times.
Another advantage of the latter system is that the provision of a separate SRAM input register coupled to an external source permits data transfers to the SRAM without going through the DRAM.
While providing a reduction in the time it takes for storing data in an SRAM from an external source, the above-described improvements in video graphic systems do not provide a method or an apparatus for resetting an SRAM and/or a DRAM in less than 25% of the time it takes to ordinarily load a DRAM in a conventional manner.